2008

Papers

  1. Fumiyo Takano, Yoshitaka Maekawa, Hironori Kasahara, "Multiple-paths Search with Concurrent Thread Scheduling for Fast AND/OR Tree Search", Proc. of International Conference on Complex, Intelligent and Software Intensive Systems (CISIS 2009), Mar. 2009.(PDF)

  2. Fumiyo Takano, Yoshitaka Maekawa, Hironori Kasahara, "Parallel and Concurrent Search for Fast AND/OR Tree Search on Multicore Processors", Proc. of the IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN 2009), Feb. 2009.(PDF)

  3. Hiroki Mikami, Jun Shirako, Masayoshi Mase, Takamichi Miyamoto, Hirofumi Nakano, Fumiyo Takano, Akihiro Hayashi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on Multicore Processors", Proc. of 14th Workshop on Compilers for Parallel Computing(CPC 2009), Jan. 2009.

  4. Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API", Proc. of IEEE International Symposium on Advances in Parallel and Distributed Computing Techniques (APDCT-08), Dec. 2008.

  5. Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "An Evaluation of Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API", IPSJ Transactions on Advanced Computing Systems, Vol. 1, No. 3, pp.83-95, Dec. 2008.

  6. Jun Shirako, Keiji Kimura, Hironori Kasahara, "Power Reduction Controll for Multicores in OSCAR Multigrain Parallelizing Compiler", Proc. of International SoC Design Conference (ISOCC 2008), Nov. 2008.

  7. Jun Shirako, Hironori Kasahara, Vivek Sarkar, "Language Extensions in Support of Compiler Parallelization", Lecture Notes in Computer Science, Springer, Vol. 5234, pp.78-94, Oct. 2008.

  8. Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture", Trans. of IPSJ on Computing Systems, Vol. 1, No. 1, pp.105-119, Jun. 2008.

  9. Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Parallelizing Compiler Cooperative Heterogeneous Multicore", Proc. of Workshop on Software and Hardware Challenges of Manycore Platforms (SHCMP 2008), Jun. 2008.

  10. Yutaka Yoshida, Masayuki Ito, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Toshihiro Hattori, Jun Sakiyama, Masashi Takada, Kunio Uchiyama, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "An 8 CPU SoC with Independent Power-off Control of CPUs and Multicore Software Debug Function", Proc. of IEEE Cool Chips XI: Symposium on Low-Power and High-Speed Chips 2008, Apr. 2008.

  11. Hiroaki Shikano, Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Heterogeneous Multi-core Architecture that Enables 54x AAC-LC Stereo Encoding", IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp.902-910, Apr. 2008.

  12. Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Power-Aware Compiler Controllable Chip Multiprocessor", IEICE TRANS. ELECTRON, Vol. E91-C, No. 4, pp.432-439, Apr. 2008.

 

Invited Talks

  1. Hironori Kasahara, "Low Power Multicores Processor and Software Technologies", Waseda University Technical Presentation Meeting, Taiwan, Mar. 2009. (pdf)  (Chinese Ver. pdf)

  2. Hironori Kasahara, "OSCAR Parallelizing Compiler and API for Low Power High Performance Multicores", The 11th International Specialist Meeting on The Next generation Models on Climate Change and Sustainability for Adavanced High-performance Computing Facilities (Climate Meeting 2009), Oak Ridge National Laboratory, USA, Mar. 2009.  (pdf)

  3. Hironori Kasahara, "Parallelizing Compiler and API for Embedded Multi-cores", TRON Association, Tokyo, Japan, Feb. 2009.(pdf)

  4. Hironori Kasahara, "Panel Discussions: Japanese Challenges for Multicore -Low Power High Performance Multicores,Compiler and API-", Intel Higher Education Program 2008 Asia Academic Forum, Taiwan, Oct. 2008.  (pdf)

  5. Hironori Kasahara, "Multicore Technologies for Realization of Low-carbon Society and Challenge for Utilization Technologies", IBM HPC Forum 2008,Tokyo, Sep. 2008. (pdf)

  6. Hironori Kasahara, "Multi-Core Technologies for Information Appliance (Parallelizing Compiler, Multi-Core API, 8CPU-LSI)  (1/2)", Microprocessor Forum Japan 2008, Aoyama Diamond Hall, Tokyo, Jul. 2008.

  7. Hironori Kasahara, "Low Power High Performance Multicores Technology", JAPAN ASSOCIATION for HEAT PIPE Seminar, Waseda Univ., Jul. 2008. (pdf)

  8. Hironori Kasahara, "OSCAR Low Power High Performance Multicore and Parallelizing Compiler", Nokia, Finland, Jun. 2008. (pdf)

  9. Hironori Kasahara, "Compiler and API for Low Power High Performance Multicores", 8th International Forum on Application-Specific Multi-Processor SoC (MpSoc '08), Valkenburg, Netherlands, Jun. 2008.   (pdf)

  10. Hironori Kasahara, "OSCAR Multigrain Parallelizing Compiler for High Performance Low Power Multicores", The 14th Workshop on Compiler Techniques for High-Performance Computing(CTHPC2008), Taiwan, May. 2008. (pdf)

  11. Hironori Kasahara, "OSCAR Multigrain Parallelizing Compiler for High Performance Low Power Multicores", Industrial Technology Research Institute, Hosted by Dr. Cheng, Taiwan, May. 2008. (pdf)

  12. Hironori Kasahara, "Embedded Multi-cores Advanced Parallelizing Compiler Technologies", 11th Embedded Systems Expo, Tokyo, Japan, May. 2008. (pdf)

  13. Hironori Kasahara, "Multicore Compiler for Low Power High Performance Embedded Computing", IEEE Symposium on Low-Power and High-Speed Chips COOLChips XI, Yokohama, Japan, Yokohama, Japan, Apr 18, 2008, 09:30-10:20 (pdf)

  14. Hironori Kasahara, "Panel Discussions: Multi-Core and Many-Core: the 5 to 10 Year View", IEEE Symposium on Low-Power and High-Speed Chips COOLChips XI, Yokohama, Japan, Apr 18, 2008, 16:10-18:10

 

Technical Reports

  1. Mamoru Shimaoka, Kazuhiro Imaizumi, Fumiyo Takano, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Minimum Execution Time Multiprocessor Scheduling Algorithms Using Standard Task Graph Set Ver3 Consider Parallelism of Task Graphs and Deviation of Task Execution Time", Technical Report of IEICE, Feb. 2009. (pdf)

  2. Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/140), Jan. 2009.   (pdf)

  3. Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Local Memory Management Scheme by a Compiler for Multicore Processor", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/141), Jan. 2009.  (pdf)

  4. Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara, "A Power Saving Scheme on Multicore Processors Using OSCAR API", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/145), Jan. 2009.   (pdf)

  5. Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Yuta Murata, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of Restricted C Programs using Pointer Analysis", Technical Report of IPSJ, May. 2008. (pdf)

  6. Kaito Yamada, Masayoshi Mase, Jun Shirako, Keiji Kimura, Masayuki Ito, Toshihiro Hattori, Hiroyuki Mizuno, Kunio Uchiyama, Hironori Kasahara, "An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping", Technical Report of IPSJ, May. 2008.(pdf)

 

Symposium

  1. Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Parallelization of Multimedia Applications by Compiler on Multicores for Consumer Electronics", Symposium on Advanced Computing Systems and Infrastructures (SACSIS 2008), May. 2008. (With Review) (pdf)

Poster Presentation

  1. Hironori Kasahara & Keiji Kimura Laboratory, "High Performance ECO Multicore Computer", TechnoFair WASEDA, Oct. 2008.

  2. Hironori Kasahara, "OSCAR Multicore Compiler for Low Power High Performance Computing", Intel Higher Education Program 2008 Asia Academic Forum, Oct. 2008.

  3. Akihiro Hayashi, Yasutaka Wada, Hiroaki Shikano, Jun Shirako, Keiji Kimura, Hironori Kasahara, "Compiler Cooperative Heterogeneous Multicore Processor", Waseda University Global COE Program the 2nd International Symposium "Ambient SoC; Recent Topics in Nano-Technology and Information Technology Applications", Jul. 2008 (pdf)

Awards

  1. Hironori Kasahara, "Intel 2008 Asia Academic Forum Best Research Award", Oct. 2008.

  2. Waseda Univ. (Prof. Hironori Kasahara), Renesas technology, Hitachi, "2008 LSI of-The-Year Second Prize", Jul. 2008.

 

Newspapers

  1. Asahi Shimbun (Newspaper), " Part2-5, Connecting Games", Feb. 06. 2009.

  2. Nikkei Sangyo Shimbun (Newspaper), "Multicore MPU for Consumer Electronics -Reduction of Consumed Power by Parallel Processing: Accomplishment by National Project-", Jan. 16. 2009.

  3. Nikkei Sangyo Shimbun (Newspaper), "Waseda Univ.: Efficient Use of Multicore MPU, Opening Program Specification to the Public", Nov. 12. 2008.

  4. Handoutai Sangyo Shimbun (Newspaper), "LSI of the Year 2008 the Second Grand Prix: LSI:RP2 Having 8CPU Cores and 8RAMs Realizing Independent Power Shut-down: Differentiates by Software Productivity and Extreme Low Consumed Power -Accomplishment by Industry-Academia Collaboration Bringing Advantageous Technologies-", Sep. 24. 2008.

  5. Handoutai Sangyo Shimbun (Newspaper), "2008 LSI of The Year The Second Prize. Innovative Low Power Consumption LSI(Renesas, Hitachi, Waseda Univ.), Jul. 16. 2008.

  6. Handoutai Sangyo Shimbun (Newspaper), "Renesas, Hitachi, Waseda Univ. Received 2008 LSI of The Year The Second Prize", Jul. 09. 2008.

  7. Nikkei Sangyo Shimbun (Newspaper), "Development of Multicore Technology for Efficient Development of Consumer Electronics, Waseda Univ.", May. 20. 2008..

Articles

  1. Hitachi Hyoron, Vol.91, No.1, pp.125, "Innovative Multicore LSI Realized Low Consumed Power and High Software Productivity", Jan. 01. 2009.

  2. EDN Japan, No.95, pp.17, "API for "OSCAR compiler" automatically generate code for multicores", Jan. 01. 2009.

  3. Nikkei Electronics, No.993, pp.107-117, "Apple Open CL Gives Prosessors Freedom", Dec. 15. 2008.

  4. Waseda University CAMPUS NOW, Vol. 183, "Selected as the Runner-Up Grand Prix of the '15th Annual LSI of the Year, 2008' ", Oct. 01. 2008.

  5. EDN Japan, No.91, pp.19-26, "Microprocessor Forum Japan: Software for multicore processor was the focal point", Sep. 01. 2008.

  6. sgi news, No.43, pp.8, "Small-Footprint, Power-Saving, and High-Performance Deskside Computer Reduces Software Development Period", Jul. 2008.

  7. Brochure about NEDO Electronic & Information Technology Development Dept. pp.13, "2. Accomplishments of 'Multicore Technology for Real Time Consumer Electronics' in Semiconductor Application Chip Project were Introduced in the Council for Science and Technology Policy as a Next Generation IT Energy Saving Technology", Jun.
    2008.

  8. EDN Japan, No.87, pp.72-73, "Highlights of ESEC2008", May. 01. 2008.

  9. Automotive Electronics, Vol.2, pp.52-55, "Upcoming Epoch of Multicore Processor", May. 01. 2008.

  10. RENESAS Edge Vol.21 pp.6, "Development of Low Power Consumption Technology of Multicore LSI for Consumer Electronics", Apr. 30. 2008.

  11. Waseda University CAMPUS NOW, Vol. 180, "Development of Low Power Consumption Technology of Multicore LSI for Consumer Electronics", Apr. 01. 2008.

  12. Hitachi Environmental Report 2008, "Development of Low Power Consumption Technology of Multicore LSI", Apr. 2008.

Web News

  1. asahi.com, "<Networking Now> Part2-5, Connecting Games", Feb. 06. 2009.

  2. Hitachi Hyoron, "Innovative Multicore LSI Realized Low Consumed Power and High Software Productivity", Jan. 01. 2009.

  3. EDN Japan MAGAZINE ARTICLES, Jan. 2009, "API for "OSCAR compiler" automatically generate code for multicores", Jan. 01. 2009.

  4. Nikkei BP Mail Magazine No.194 -Emerging Technology Business-, "Realization of Japanese Style Industry Academia Collaboration Management", Dec. 17. 2008.

  5. Nikkei Electronics Tech On, "Waseda Univ. & Japanese Semi Conductor Companies Developped Standard API to Direct Parallel Execution and Power Control to Compilers", Nov. 14. 2008.

  6. Nikkei Electronics Tech On, "Group Develops Standard API to Give Parallel Execution, Power Control Orders to Compiler", Nov. 16. 2008.

  7. Nikkei BP Emerging Technology Business, "Prof. Kasahara, Waseda Univ Developed API for Real-time Parallel Processing in a National Project with 6 companies and Opened it to the Public in Nov. 2008", Nov. 14. 2008.

  8. Nikkei Shushoku Navi, "Waseda Univ.: Efficient Use of Multicore MPU, Opening Program Specification to the Public", Nov. 12. 2008.

  9. NIKKEI NET, "Waseda Univ.: Efficient Use of Multicore MPU, Opening Program Specification to the Public", Nov. 12. 2008.

  10. NIKKEI NET, "Waseda University et al. Deverop and Open API realizing Low Consumed Power Real-time Parallel Processing", Nov. 11. 2008.

  11. NIKKEI NET IT PLUS, "Waseda University et al. Deverop and Open API realizing Low Consumed Power Real-time Parallel Processing", Nov. 11. 2008.

  12. TRENDLINE, "Waseda University et al. Deverop and Open API realizing Low Consumed Power Real-time Parallel Processing", Nov. 11. 2008.

  13. Faculty of Science and Engineering, Waseda Univ. HP, "Public Release of OSCAR API, Prof. Kasahara, Waseda Univ.", Nov. 26. 2008.

  14. IEEE Computer Society "IEEE Computer Society Election, IEEE Computer Society Officers and Board of Governors Positions in 2009", Oct. 2008.

  15. WASEDA ONLINE (YOMIURI ONLINE) Campus Now, "Selected as the Runner-Up Grand Prix of the '15th Annual LSI of the Year, 2008' ", Oct. 01. 2008.

  16. EDN Japan MAGAZINE ARTICLES, Sep. 2008, "Microprocessor Forum Japan: Software for multicore processor was the focal point", Sep. 01. 2008.

  17. innovations report "ECO Computer by Solar Battery– Leading edge multicore technology", Jul. 15. 2008.

  18. Handoutai Sangyo Shimbun HP, "2008 LSI of the Year", Jul. 09. 2008.

  19. WASEDA ONLINE (YOMIURI ONLINE), "ECO Computer by Solar Battery – Leading edge multicore technology –", Jul. 07. 2008.

  20. MYCOM Journal, "2008 LSI of the Year", Jul. 04. 2008.

  21. Denshi Journal, "2008 LSI of the Year", Jul. 04. 2008.  

  22. Waseda University HP, "Multicore LSI Developed by Waseda Univ., Hitachi, and Renesas Won 2008 LSI of-The-Year Second Prize", Jul. 04. 2008.

  23. @IT MONOist, ”Microprocessor Forum Japan 2008, A Highlight is Advanced Technology of Processor for Small Devices.", Jul. 01. 2008.

  24. Electronics Design, Strategy, News -Leibson's Law- "MPSOC ’08, Live from Maastricht: Got SMP? Need Auto Parallelization? Just add Multigrain OSCAR", Jul. 01. 2008.

  25. SGI e-News, "Case Introduction, Dept. of Computer Science, Waseda Univ.: Parallelizing Compiler Research for Multicore Processor. SGI Japan Installed Mid Range Servers "Altix 450" to Kasahara Lab, Waseda Univ. : Small-Footprint, Power-Saving, and High-Performance Deskside Computer Reduce Software Development Period", Jun. 18. 2008.

  26. Digital New Deal, "Mr. Bunro Shiozawa's Style: Trip to the Beginning, No.32 -A Lecture Place is also a Development Place", May. 28. 2008.

  27. MYCOM Journal, "Cool Chips XI -Panel Discussion-", May. 21. 2008.

  28. MYCOM Journal, "Cool Chips XI -Multicore Compiler Realizing Power-Saving and High-Performance-", May. 11. 2008.

  29. MYCOM Journal, "Cool Chips XI -Remarkable Papers-", May. 01. 2008.

  30. Automotive Electronics Feature, "Upcoming Epoch of Multicore Processor", May. 11. 2008.

  31. IPSJ Special Interest Group on Computer Architecture: Panel Discussion "Multicore Strategy of a New Era" (Dr. Fukunaga, Hitachi) , "Situation of Research of Multicore CPU and Expectation from User View", May. 13. 2008.

  32. Waseda Univ. CAMPUS NOW Online, "Development of Low Power Consumption Technology of Multicore LSI for Consumer Electronics", Apr. 16. 2008.

  33. Council for Science and Technology Policy 74th session , (Developed multicore was introduced in the CSTP at the Prime Minister's Office on April 10, 2008), Apr. 10. 2008.
     

Press Release

  1. Waseda University Press Release, "Software Standard (API) Realizing Low Power Real-time Parallel Processing on Multicores for Consumer Electronics from Different Vendors", Nov. 11. 2008.

Patents

 Registration of patent

  1. "GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR", 10-0878917 (KR Patent), Jan. 08. 2009.

  2. "MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER", 10-0861631 (KR Patent), Sep. 26. 2008.

  3. "COMPILE METHOD, COMPILER AND COMPILE DEVICE", 4177681, Aug. 29. 2008.

 Published applications for patent

  1. "LOCAL MEMORY MANAGEMENT, INFORMATION-PROCESSING DEVICE, PROGRAM CREATION METHOD AND PROGRAM", 2008-217134 (JP Publication), Sep. 18. 2008.

  2. "MULTIPROCESSOR ", 2008-217825 (JP Publication), Sep. 18. 2008. 【Registration of patent: 4304347 (JP Publication), May. 15. 2009.】

  3. "LOCAL MEMORY MANAGEMENT, INFORMATION-PROCESSING DEVICE, PROGRAM CREATION METHOD AND PROGRAM", WO/2008/105558(WO Publication), Sep. 04. 2008.

  4. "MULTIPROCESSOR AND MULTIPROCESSOR SYSTEM", 2008-181558 (JP Publication), Aug. 07. 2008. 【Registration of patent: 4784842 (JP Publication), Jul. 22. 2011】

  5. "PROCESSOR AND DATA TRANSFER UNIT ", 2008-097084 (JP Publication), Apr. 24. 2008. 【Registration of patent:4476267 (JP Publication), Mar. 19. 2010】

  6. "PROCESSOR AND DATA TRANSFER UNIT ", US-2008-086617 (US Publication), Apr. 10. 2008. 【Registration of patent:8200934 (US Patent), Jun. 12. 2012.】